1. Technical Field of the Invention
The present invention relates to a reference current generator for memory devices, and particularly to circuitry for more effectively generating a reference current in nonvolatile memory devices.

2. Description of the Related Art
The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term xe2x80x9chot carriersxe2x80x9d). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a xe2x80x9cprogrammedxe2x80x9d state.
The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration. By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.
In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.
A third type of memory has more recently gained popularity. This type of memory, flash EPROMs, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.
Flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array of flash memory cells organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to the column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines based upon the data values stored in the addressed flash memory cells. The particular implementations of the array and the row and column decoders are known in the art and will not be described further for reasons of simplicity.
A conventional sense amplifier circuit includes a differential amplifier circuit that generally senses a voltage differential between the voltage appearing on a column line connected to a reference cell and the voltage appearing on a reference node and the voltage appearing on a column line connected to an addressed memory cell, and drives a sense output signal (that is coupled to the data output pins of the flash memory device) based upon the sensed voltage differential.
Conventional flash memory devices include a reference current generator for generating a reference current for use by the sense amplifier circuits. A current mirror circuit in the flash memory device mirrors the reference current and applies a single mirrored reference current to all of the sense amplifiers. A startup circuit is utilized in some existing flash memory devices in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. An existing startup circuit includes first and second discharge current stages, with each discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. Each discharge current stage utilizes feedback to gradually decrease the rate of discharge by the discharge current stage so that the discharge current stages are disabled by the time the voltage appearing at the reference node input of the sense amplifiers reaches the desired voltage level.
The known reference current generator and startup circuits, however, have shortcomings. For instance, the use of the reference current generator and corresponding current mirror circuit limits the number of sense amplifiers that may be utilized at one time. There is a relatively slow settling time of the reference voltage due to the large capacitive loading on the reference current generator/mirror circuit when a large number of sense amplifiers are used. In addition, the limitation exists due to the amount of noise introduced within each sense amplifier that may affect data integrity. As a result, certain flash memory device features, such as burst mode and page mode features, cannot be effectively executed in conventional flash memory devices.
Based upon the foregoing, there is a need to more effectively and accurately provide reference current levels to sense amplifiers in a nonvolatile memory device, such as a flash memory device.
Embodiments of the present invention overcome shortcomings in prior flash memory devices and satisfy a significant need for a nonvolatile memory device, such as a flash memory device, that quickly and efficiently provides a reference current to sense amplifiers in the nonvolatile memory device.
In an exemplary embodiment of the present invention, the nonvolatile memory device includes a reference generator circuit for generating a reference current for application to the reference input of the sense amplifiers in the nonvolatile memory device. A bandgap reference circuit generates a bandgap voltage reference. At least one startup circuit initially sets the reference input of the sense amplifiers to a predetermined voltage level. The startup circuit allows for a relatively quick settling of the reference input to the desired predetermined voltage level.
The startup circuit includes a first circuit stage coupled to the bandgap reference circuit for receiving a bandgap current generated from the bandgap voltage reference. The first circuit stage discharges a charge appearing on the reference input of the sense amplifiers from an initial voltage level, such as the supply voltage Vdd, to a voltage level greater than the predetermined voltage level, a rate of discharge being based upon the received bandgap current. The startup circuit further includes a second circuit stage coupled to the reference generator circuit and including a second discharge circuit for discharging a charge appearing on the reference input of the sense amplifiers from the initial voltage level towards the predetermined voltage level, a rate of discharge being based upon the reference current. By basing the rate of discharge of the second discharge circuit upon the reference current, the startup circuit is better matched to the reference generator circuit across process and operational corners.
For flash memory devices having a relatively large number of sense amplifiers, a current buffer circuit may be disposed between the output of the reference generator circuit and the reference inputs of the sense amplifiers. In this case, the current buffer circuit may be implemented as current mirror circuitry having a first circuit leg and a plurality of second circuit legs. The reference current provided by the reference current generator passes through the first circuit leg. The reference current is thereby mirrored in each second circuit leg. Each second circuit leg provides the mirrored reference current to a distinct set of sense amplifiers. In this way, the reference current generated by the reference current generator has lower capacitive load so as to provide a faster settling time. The reference current generator is also isolated from coupling noise associated with the sense amplifiers, which may approach nontrivial levels for a nonvolatile memory device having many sense amplifiers.